/* SPDX-License-Identifier: GPL-2.0+ */
// $Module: reg_PHY_IP_MUX $
// $RegisterBank Version: v1.0.00 $
// $Author:  $
// $Date: Tue, 28 Feb 2023 09:49:18 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  PHY_IP_MUX_REG_GRP_VI2_CLK0_SEL  0x0
#define  PHY_IP_MUX_REG_GRP_GPIO138_SEL  0x4
#define  PHY_IP_MUX_REG_GRP_DEBUG_0_SEL  0x8
#define  PHY_IP_MUX_REG_GRP_VI2_D8_SEL  0xc
#define  PHY_IP_MUX_REG_GRP_GPIO139_SEL  0x10
#define  PHY_IP_MUX_REG_GRP_DEBUG_1_SEL  0x14
#define  PHY_IP_MUX_REG_GRP_VI2_D9_SEL  0x18
#define  PHY_IP_MUX_REG_GRP_GPIO140_SEL  0x1c
#define  PHY_IP_MUX_REG_GRP_DEBUG_2_SEL  0x20
#define  PHY_IP_MUX_REG_GRP_VI2_D10_SEL  0x24
#define  PHY_IP_MUX_REG_GRP_GPIO141_SEL  0x28
#define  PHY_IP_MUX_REG_GRP_DEBUG_3_SEL  0x2c
#define  PHY_IP_MUX_REG_GRP_VI2_D0_SEL  0x30
#define  PHY_IP_MUX_REG_GRP_GPIO142_SEL  0x34
#define  PHY_IP_MUX_REG_GRP_DEBUG_4_SEL  0x38
#define  PHY_IP_MUX_REG_GRP_VI2_D1_SEL  0x3c
#define  PHY_IP_MUX_REG_GRP_GPIO143_SEL  0x40
#define  PHY_IP_MUX_REG_GRP_DEBUG_5_SEL  0x44
#define  PHY_IP_MUX_REG_GRP_VI2_D2_SEL  0x48
#define  PHY_IP_MUX_REG_GRP_VI1_D13_SEL  0x4c
#define  PHY_IP_MUX_REG_GRP_GPIO144_SEL  0x50
#define  PHY_IP_MUX_REG_GRP_DEBUG_6_SEL  0x54
#define  PHY_IP_MUX_REG_GRP_VI0_D19_SEL  0x58
#define  PHY_IP_MUX_REG_GRP_IIC1_SDA_SEL  0x5c
#define  PHY_IP_MUX_REG_GRP_VI2_D3_SEL  0x60
#define  PHY_IP_MUX_REG_GRP_VI1_D12_SEL  0x64
#define  PHY_IP_MUX_REG_GRP_GPIO145_SEL  0x68
#define  PHY_IP_MUX_REG_GRP_DEBUG_7_SEL  0x6c
#define  PHY_IP_MUX_REG_GRP_VI0_D20_SEL  0x70
#define  PHY_IP_MUX_REG_GRP_IIC1_SCL_SEL  0x74
#define  PHY_IP_MUX_REG_GRP_VI2_D4_SEL  0x78
#define  PHY_IP_MUX_REG_GRP_VI1_D11_SEL  0x7c
#define  PHY_IP_MUX_REG_GRP_GPIO146_SEL  0x80
#define  PHY_IP_MUX_REG_GRP_DEBUG_8_SEL  0x84
#define  PHY_IP_MUX_REG_GRP_VI0_D21_SEL  0x88
#define  PHY_IP_MUX_REG_GRP_VI2_D5_SEL  0x8c
#define  PHY_IP_MUX_REG_GRP_VI1_D10_SEL  0x90
#define  PHY_IP_MUX_REG_GRP_GPIO147_SEL  0x94
#define  PHY_IP_MUX_REG_GRP_DEBUG_9_SEL  0x98
#define  PHY_IP_MUX_REG_GRP_VI0_D22_SEL  0x9c
#define  PHY_IP_MUX_REG_GRP_VI2_D6_SEL  0xa0
#define  PHY_IP_MUX_REG_GRP_VI1_D9_SEL  0xa4
#define  PHY_IP_MUX_REG_GRP_GPIO148_SEL  0xa8
#define  PHY_IP_MUX_REG_GRP_DEBUG_10_SEL  0xac
#define  PHY_IP_MUX_REG_GRP_VI0_D23_SEL  0xb0
#define  PHY_IP_MUX_REG_GRP_CAM_MCLK0_SEL  0xb4
#define  PHY_IP_MUX_REG_GRP_VI2_D7_SEL  0xb8
#define  PHY_IP_MUX_REG_GRP_VI1_D8_SEL  0xbc
#define  PHY_IP_MUX_REG_GRP_GPIO149_SEL  0xc0
#define  PHY_IP_MUX_REG_GRP_DEBUG_11_SEL  0xc4
#define  PHY_IP_MUX_REG_GRP_VI0_D24_SEL  0xc8
#define  PHY_IP_MUX_REG_GRP_CAM_MCLK1_SEL  0xcc
#define  PHY_IP_MUX_REG_GRP_VI1_CLK0_SEL  0xd0
#define  PHY_IP_MUX_REG_GRP_GPIO150_SEL  0xd4
#define  PHY_IP_MUX_REG_GRP_DEBUG_12_SEL  0xd8
#define  PHY_IP_MUX_REG_GRP_VI0_CLK0_SEL  0xdc
#define  PHY_IP_MUX_REG_GRP_CAM_MCLK2_SEL  0xe0
#define  PHY_IP_MUX_REG_GRP_CAM_HS0_SEL  0xe4
#define  PHY_IP_MUX_REG_GRP_VI1_D14_SEL  0xe8
#define  PHY_IP_MUX_REG_GRP_GPIO151_SEL  0xec
#define  PHY_IP_MUX_REG_GRP_DEBUG_13_SEL  0xf0
#define  PHY_IP_MUX_REG_GRP_VI0_D25_SEL  0xf4
#define  PHY_IP_MUX_REG_GRP_CAM_MCLK3_SEL  0xf8
#define  PHY_IP_MUX_REG_GRP_CAM_VS0_SEL  0xfc
#define  PHY_IP_MUX_REG_GRP_VI1_D15_SEL  0x100
#define  PHY_IP_MUX_REG_GRP_GPIO152_SEL  0x104
#define  PHY_IP_MUX_REG_GRP_DEBUG_14_SEL  0x108
#define  PHY_IP_MUX_REG_GRP_VI0_D26_SEL  0x10c
#define  PHY_IP_MUX_REG_GRP_CAM_HS1_SEL  0x110
#define  PHY_IP_MUX_REG_GRP_VI1_D16_SEL  0x114
#define  PHY_IP_MUX_REG_GRP_GPIO153_SEL  0x118
#define  PHY_IP_MUX_REG_GRP_DEBUG_15_SEL  0x11c
#define  PHY_IP_MUX_REG_GRP_VI0_D27_SEL  0x120
#define  PHY_IP_MUX_REG_GRP_CAM_VS1_SEL  0x124
#define  PHY_IP_MUX_REG_GRP_VI1_D0_SEL  0x128
#define  PHY_IP_MUX_REG_GRP_GPIO154_SEL  0x12c
#define  PHY_IP_MUX_REG_GRP_DEBUG_16_SEL  0x130
#define  PHY_IP_MUX_REG_GRP_VI0_D15_SEL  0x134
#define  PHY_IP_MUX_REG_GRP_CAM_HS2_SEL  0x138
#define  PHY_IP_MUX_REG_GRP_VI1_D1_SEL  0x13c
#define  PHY_IP_MUX_REG_GRP_GPIO155_SEL  0x140
#define  PHY_IP_MUX_REG_GRP_DEBUG_17_SEL  0x144
#define  PHY_IP_MUX_REG_GRP_VI0_D14_SEL  0x148
#define  PHY_IP_MUX_REG_GRP_CAM_VS2_SEL  0x14c
#define  PHY_IP_MUX_REG_GRP_VI1_D2_SEL  0x150
#define  PHY_IP_MUX_REG_GRP_GPIO156_SEL  0x154
#define  PHY_IP_MUX_REG_GRP_DEBUG_18_SEL  0x158
#define  PHY_IP_MUX_REG_GRP_VI0_D13_SEL  0x15c
#define  PHY_IP_MUX_REG_GRP_IIC2_SDA_SEL  0x160
#define  PHY_IP_MUX_REG_GRP_VI1_D3_SEL  0x164
#define  PHY_IP_MUX_REG_GRP_GPIO157_SEL  0x168
#define  PHY_IP_MUX_REG_GRP_DEBUG_19_SEL  0x16c
#define  PHY_IP_MUX_REG_GRP_VI0_D12_SEL  0x170
#define  PHY_IP_MUX_REG_GRP_IIC2_SCL_SEL  0x174
#define  PHY_IP_MUX_REG_GRP_VI1_D4_SEL  0x178
#define  PHY_IP_MUX_REG_GRP_GPIO158_SEL  0x17c
#define  PHY_IP_MUX_REG_GRP_DEBUG_20_SEL  0x180
#define  PHY_IP_MUX_REG_GRP_VI0_D11_SEL  0x184
#define  PHY_IP_MUX_REG_GRP_IIC4_SDA_SEL  0x188
#define  PHY_IP_MUX_REG_GRP_VI1_D5_SEL  0x18c
#define  PHY_IP_MUX_REG_GRP_DEBUG_21_SEL  0x190
#define  PHY_IP_MUX_REG_GRP_VI0_D10_SEL  0x194
#define  PHY_IP_MUX_REG_GRP_IIC4_SCL_SEL  0x198
#define  PHY_IP_MUX_REG_GRP_VI1_D6_SEL  0x19c
#define  PHY_IP_MUX_REG_GRP_GPIO160_SEL  0x1a0
#define  PHY_IP_MUX_REG_GRP_DEBUG_22_SEL  0x1a4
#define  PHY_IP_MUX_REG_GRP_VI0_D9_SEL  0x1a8
#define  PHY_IP_MUX_REG_GRP_VI1_D7_SEL  0x1ac
#define  PHY_IP_MUX_REG_GRP_GPIO161_SEL  0x1b0
#define  PHY_IP_MUX_REG_GRP_DEBUG_23_SEL  0x1b4
#define  PHY_IP_MUX_REG_GRP_VI0_D8_SEL  0x1b8
#define  PHY_IP_MUX_REG_GRP_GPIO162_SEL  0x1bc
#define  PHY_IP_MUX_REG_GRP_DEBUG_24_SEL  0x1c0
#define  PHY_IP_MUX_REG_GRP_GPIO163_SEL  0x1c4
#define  PHY_IP_MUX_REG_GRP_DEBUG_25_SEL  0x1c8
#define  PHY_IP_MUX_REG_GRP_VI0_D16_SEL  0x1cc
#define  PHY_IP_MUX_REG_GRP_GPIO164_SEL  0x1d0
#define  PHY_IP_MUX_REG_GRP_DEBUG_26_SEL  0x1d4
#define  PHY_IP_MUX_REG_GRP_VI0_D17_SEL  0x1d8
#define  PHY_IP_MUX_REG_GRP_GPIO165_SEL  0x1dc
#define  PHY_IP_MUX_REG_GRP_DEBUG_27_SEL  0x1e0
#define  PHY_IP_MUX_REG_GRP_VI0_D18_SEL  0x1e4
#define  PHY_IP_MUX_REG_GRP_GPIO166_SEL  0x1e8
#define  PHY_IP_MUX_REG_GRP_DEBUG_28_SEL  0x1ec
#define  PHY_IP_MUX_REG_GRP_VI0_D0_SEL  0x1f0
#define  PHY_IP_MUX_REG_GRP_GPIO167_SEL  0x1f4
#define  PHY_IP_MUX_REG_GRP_DEBUG_29_SEL  0x1f8
#define  PHY_IP_MUX_REG_GRP_VI0_D1_SEL  0x1fc
#define  PHY_IP_MUX_REG_GRP_GPIO168_SEL  0x200
#define  PHY_IP_MUX_REG_GRP_DEBUG_30_SEL  0x204
#define  PHY_IP_MUX_REG_GRP_VI0_D2_SEL  0x208
#define  PHY_IP_MUX_REG_GRP_GPIO169_SEL  0x20c
#define  PHY_IP_MUX_REG_GRP_DEBUG_31_SEL  0x210
#define  PHY_IP_MUX_REG_GRP_VI0_D3_SEL  0x214
#define  PHY_IP_MUX_REG_GRP_GPIO170_SEL  0x218
#define  PHY_IP_MUX_REG_GRP_VI0_D4_SEL  0x21c
#define  PHY_IP_MUX_REG_GRP_GPIO171_SEL  0x220
#define  PHY_IP_MUX_REG_GRP_VI0_D5_SEL  0x224
#define  PHY_IP_MUX_REG_GRP_GPIO172_SEL  0x228
#define  PHY_IP_MUX_REG_GRP_VI0_D6_SEL  0x22c
#define  PHY_IP_MUX_REG_GRP_CAM_MCLK4_SEL  0x230
#define  PHY_IP_MUX_REG_GRP_GPIO173_SEL  0x234
#define  PHY_IP_MUX_REG_GRP_VI0_D7_SEL  0x238
#define  PHY_IP_MUX_REG_GRP_CAM_MCLK5_SEL  0x23c
#define  PHY_IP_MUX_REG_GRP_VO0_D14_SEL  0x240
#define  PHY_IP_MUX_REG_GRP_GPIO174_SEL  0x244
#define  PHY_IP_MUX_REG_GRP_IIC5_SDA_SEL  0x248
#define  PHY_IP_MUX_REG_GRP_VO1_D14_SEL  0x24c
#define  PHY_IP_MUX_REG_GRP_VO0_D15_SEL  0x250
#define  PHY_IP_MUX_REG_GRP_GPIO175_SEL  0x254
#define  PHY_IP_MUX_REG_GRP_IIC5_SCL_SEL  0x258
#define  PHY_IP_MUX_REG_GRP_VO1_D15_SEL  0x25c
#define  PHY_IP_MUX_REG_GRP_VO0_D16_SEL  0x260
#define  PHY_IP_MUX_REG_GRP_GPIO176_SEL  0x264
#define  PHY_IP_MUX_REG_GRP_IIC6_SDA_SEL  0x268
#define  PHY_IP_MUX_REG_GRP_VO1_D16_SEL  0x26c
#define  PHY_IP_MUX_REG_GRP_VO0_D17_SEL  0x270
#define  PHY_IP_MUX_REG_GRP_GPIO177_SEL  0x274
#define  PHY_IP_MUX_REG_GRP_IIC6_SCL_SEL  0x278
#define  PHY_IP_MUX_REG_GRP_VO1_D17_SEL  0x27c
#define  PHY_IP_MUX_REG_GRP_VO0_D18_SEL  0x280
#define  PHY_IP_MUX_REG_GRP_GPIO178_SEL  0x284
#define  PHY_IP_MUX_REG_GRP_IIC7_SDA_SEL  0x288
#define  PHY_IP_MUX_REG_GRP_VO1_D18_SEL  0x28c
#define  PHY_IP_MUX_REG_GRP_VO0_D19_SEL  0x290
#define  PHY_IP_MUX_REG_GRP_GPIO179_SEL  0x294
#define  PHY_IP_MUX_REG_GRP_IIC7_SCL_SEL  0x298
#define  PHY_IP_MUX_REG_GRP_VO1_D19_SEL  0x29c
#define  PHY_IP_MUX_REG_GRP_VO0_D20_SEL  0x2a0
#define  PHY_IP_MUX_REG_GRP_GPIO180_SEL  0x2a4
#define  PHY_IP_MUX_REG_GRP_IIC8_SDA_SEL  0x2a8
#define  PHY_IP_MUX_REG_GRP_VO1_D20_SEL  0x2ac
#define  PHY_IP_MUX_REG_GRP_VO0_D21_SEL  0x2b0
#define  PHY_IP_MUX_REG_GRP_GPIO181_SEL  0x2b4
#define  PHY_IP_MUX_REG_GRP_IIC8_SCL_SEL  0x2b8
#define  PHY_IP_MUX_REG_GRP_VO1_D21_SEL  0x2bc
#define  PHY_IP_MUX_REG_GRP_VO0_D22_SEL  0x2c0
#define  PHY_IP_MUX_REG_GRP_GPIO182_SEL  0x2c4
#define  PHY_IP_MUX_REG_GRP_IIC9_SDA_SEL  0x2c8
#define  PHY_IP_MUX_REG_GRP_VO1_D22_SEL  0x2cc
#define  PHY_IP_MUX_REG_GRP_VO0_D23_SEL  0x2d0
#define  PHY_IP_MUX_REG_GRP_GPIO183_SEL  0x2d4
#define  PHY_IP_MUX_REG_GRP_IIC9_SCL_SEL  0x2d8
#define  PHY_IP_MUX_REG_GRP_VO1_D23_SEL  0x2dc
#define  PHY_IP_MUX_REG_GRP_VO0_D24_SEL  0x2e0
#define  PHY_IP_MUX_REG_GRP_I2S1_SCLK_SEL  0x2e4
#define  PHY_IP_MUX_REG_GRP_GPIO185_SEL  0x2e8
#define  PHY_IP_MUX_REG_GRP_UART1_TX_SEL  0x2ec
#define  PHY_IP_MUX_REG_GRP_SPI1_SDI_SEL  0x2f0
#define  PHY_IP_MUX_REG_GRP_VO1_D24_SEL  0x2f4
#define  PHY_IP_MUX_REG_GRP_VO0_D25_SEL  0x2f8
#define  PHY_IP_MUX_REG_GRP_I2S1_WSI_SEL  0x2fc
#define  PHY_IP_MUX_REG_GRP_GPIO186_SEL  0x300
#define  PHY_IP_MUX_REG_GRP_UART1_RX_SEL  0x304
#define  PHY_IP_MUX_REG_GRP_SPI1_SDO_SEL  0x308
#define  PHY_IP_MUX_REG_GRP_VO1_D25_SEL  0x30c
#define  PHY_IP_MUX_REG_GRP_VO0_D26_SEL  0x310
#define  PHY_IP_MUX_REG_GRP_I2S1_SDI_SEL  0x314
#define  PHY_IP_MUX_REG_GRP_GPIO187_SEL  0x318
#define  PHY_IP_MUX_REG_GRP_UART1_RTS_SEL  0x31c
#define  PHY_IP_MUX_REG_GRP_SPI1_SCK_SEL  0x320
#define  PHY_IP_MUX_REG_GRP_VO1_D26_SEL  0x324
#define  PHY_IP_MUX_REG_GRP_VO0_D0_SEL  0x328
#define  PHY_IP_MUX_REG_GRP_I2S1_SDO_SEL  0x32c
#define  PHY_IP_MUX_REG_GRP_GPIO188_SEL  0x330
#define  PHY_IP_MUX_REG_GRP_UART1_CTS_SEL  0x334
#define  PHY_IP_MUX_REG_GRP_SPI2_CS_X_SEL  0x338
#define  PHY_IP_MUX_REG_GRP_VO1_D0_SEL  0x33c
#define  PHY_IP_MUX_REG_GRP_VO0_D1_SEL  0x340
#define  PHY_IP_MUX_REG_GRP_I2S1_MCLK_SEL  0x344
#define  PHY_IP_MUX_REG_GRP_GPIO189_SEL  0x348
#define  PHY_IP_MUX_REG_GRP_UART2_TX_SEL  0x34c
#define  PHY_IP_MUX_REG_GRP_SPI2_SDI_SEL  0x350
#define  PHY_IP_MUX_REG_GRP_VO1_D1_SEL  0x354
#define  PHY_IP_MUX_REG_GRP_VO0_D2_SEL  0x358
#define  PHY_IP_MUX_REG_GRP_I2S2_MCLK_SEL  0x35c
#define  PHY_IP_MUX_REG_GRP_GPIO190_SEL  0x360
#define  PHY_IP_MUX_REG_GRP_UART2_RX_SEL  0x364
#define  PHY_IP_MUX_REG_GRP_SPI2_SDO_SEL  0x368
#define  PHY_IP_MUX_REG_GRP_VO1_D2_SEL  0x36c
#define  PHY_IP_MUX_REG_GRP_VO0_D3_SEL  0x370
#define  PHY_IP_MUX_REG_GRP_I2S2_SCLK_SEL  0x374
#define  PHY_IP_MUX_REG_GRP_GPIO124_SEL  0x378
#define  PHY_IP_MUX_REG_GRP_UART3_TX_SEL  0x37c
#define  PHY_IP_MUX_REG_GRP_SPI2_SCK_SEL  0x380
#define  PHY_IP_MUX_REG_GRP_SPI3_SCK_SEL  0x384
#define  PHY_IP_MUX_REG_GRP_VO1_D3_SEL  0x388
#define  PHY_IP_MUX_REG_GRP_VO0_D4_SEL  0x38c
#define  PHY_IP_MUX_REG_GRP_I2S2_WSI_SEL  0x390
#define  PHY_IP_MUX_REG_GRP_GPIO125_SEL  0x394
#define  PHY_IP_MUX_REG_GRP_UART3_RX_SEL  0x398
#define  PHY_IP_MUX_REG_GRP_SPI3_CS_X_SEL  0x39c
#define  PHY_IP_MUX_REG_GRP_SPI1_CS_X_SEL  0x3a0
#define  PHY_IP_MUX_REG_GRP_VO1_D4_SEL  0x3a4
#define  PHY_IP_MUX_REG_GRP_VO0_D5_SEL  0x3a8
#define  PHY_IP_MUX_REG_GRP_I2S2_SDI_SEL  0x3ac
#define  PHY_IP_MUX_REG_GRP_GPIO126_SEL  0x3b0
#define  PHY_IP_MUX_REG_GRP_WG1_D1_SEL  0x3b4
#define  PHY_IP_MUX_REG_GRP_SPI3_SDI_SEL  0x3b8
#define  PHY_IP_MUX_REG_GRP_IIC3_SDA_SEL  0x3bc
#define  PHY_IP_MUX_REG_GRP_VO1_D5_SEL  0x3c0
#define  PHY_IP_MUX_REG_GRP_VO0_D6_SEL  0x3c4
#define  PHY_IP_MUX_REG_GRP_I2S2_SDO_SEL  0x3c8
#define  PHY_IP_MUX_REG_GRP_GPIO127_SEL  0x3cc
#define  PHY_IP_MUX_REG_GRP_WG1_D0_SEL  0x3d0
#define  PHY_IP_MUX_REG_GRP_SPI3_SDO_SEL  0x3d4
#define  PHY_IP_MUX_REG_GRP_IIC3_SCL_SEL  0x3d8
#define  PHY_IP_MUX_REG_GRP_VO1_D6_SEL  0x3dc
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_CLK0   0x0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_CLK0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_CLK0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_CLK0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO138   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO138_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO138_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO138_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_0   0x8
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D8   0xc
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D8_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D8_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D8_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO139   0x10
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO139_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO139_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO139_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_1   0x14
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_1_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_1_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_1_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D9   0x18
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D9_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D9_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D9_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO140   0x1c
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO140_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO140_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO140_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_2   0x20
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_2_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_2_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_2_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D10   0x24
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D10_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D10_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D10_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO141   0x28
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO141_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO141_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO141_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_3   0x2c
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_3_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_3_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_3_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D0   0x30
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO142   0x34
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO142_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO142_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO142_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_4   0x38
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_4_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_4_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_4_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D1   0x3c
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D1_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D1_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D1_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO143   0x40
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO143_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO143_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO143_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_5   0x44
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_5_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_5_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_5_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D2   0x48
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D2_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D2_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D2_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D13   0x4c
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D13_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D13_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D13_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO144   0x50
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO144_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO144_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO144_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_6   0x54
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_6_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_6_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_6_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D19   0x58
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D19_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D19_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D19_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC1_SDA   0x5c
#define  PHY_IP_MUX_REG_GRP_SEL_IIC1_SDA_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC1_SDA_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC1_SDA_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D3   0x60
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D3_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D3_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D3_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D12   0x64
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D12_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D12_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D12_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO145   0x68
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO145_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO145_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO145_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_7   0x6c
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_7_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_7_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_7_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D20   0x70
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D20_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D20_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D20_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC1_SCL   0x74
#define  PHY_IP_MUX_REG_GRP_SEL_IIC1_SCL_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC1_SCL_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC1_SCL_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D4   0x78
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D4_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D4_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D4_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D11   0x7c
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D11_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D11_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D11_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO146   0x80
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO146_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO146_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO146_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_8   0x84
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_8_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_8_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_8_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D21   0x88
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D21_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D21_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D21_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D5   0x8c
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D5_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D5_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D5_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D10   0x90
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D10_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D10_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D10_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO147   0x94
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO147_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO147_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO147_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_9   0x98
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_9_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_9_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_9_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D22   0x9c
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D22_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D22_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D22_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D6   0xa0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D6_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D6_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D6_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D9   0xa4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D9_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D9_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D9_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO148   0xa8
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO148_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO148_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO148_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_10   0xac
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_10_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_10_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_10_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D23   0xb0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D23_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D23_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D23_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK0   0xb4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D7   0xb8
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D7_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D7_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI2_D7_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D8   0xbc
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D8_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D8_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D8_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO149   0xc0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO149_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO149_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO149_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_11   0xc4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_11_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_11_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_11_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D24   0xc8
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D24_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D24_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D24_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK1   0xcc
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK1_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK1_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK1_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_CLK0   0xd0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_CLK0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_CLK0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_CLK0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO150   0xd4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO150_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO150_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO150_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_12   0xd8
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_12_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_12_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_12_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_CLK0   0xdc
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_CLK0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_CLK0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_CLK0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK2   0xe0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK2_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK2_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK2_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS0   0xe4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D14   0xe8
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D14_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D14_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D14_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO151   0xec
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO151_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO151_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO151_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_13   0xf0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_13_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_13_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_13_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D25   0xf4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D25_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D25_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D25_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK3   0xf8
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK3_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK3_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK3_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS0   0xfc
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D15   0x100
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D15_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D15_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D15_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO152   0x104
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO152_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO152_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO152_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_14   0x108
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_14_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_14_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_14_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D26   0x10c
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D26_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D26_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D26_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS1   0x110
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS1_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS1_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS1_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D16   0x114
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D16_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D16_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D16_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO153   0x118
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO153_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO153_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO153_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_15   0x11c
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_15_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_15_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_15_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D27   0x120
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D27_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D27_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D27_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS1   0x124
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS1_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS1_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS1_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D0   0x128
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO154   0x12c
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO154_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO154_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO154_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_16   0x130
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_16_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_16_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_16_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D15   0x134
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D15_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D15_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D15_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS2   0x138
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS2_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS2_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_HS2_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D1   0x13c
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D1_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D1_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D1_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO155   0x140
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO155_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO155_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO155_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_17   0x144
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_17_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_17_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_17_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D14   0x148
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D14_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D14_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D14_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS2   0x14c
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS2_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS2_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_VS2_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D2   0x150
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D2_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D2_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D2_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO156   0x154
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO156_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO156_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO156_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_18   0x158
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_18_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_18_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_18_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D13   0x15c
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D13_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D13_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D13_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC2_SDA   0x160
#define  PHY_IP_MUX_REG_GRP_SEL_IIC2_SDA_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC2_SDA_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC2_SDA_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D3   0x164
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D3_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D3_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D3_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO157   0x168
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO157_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO157_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO157_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_19   0x16c
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_19_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_19_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_19_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D12   0x170
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D12_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D12_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D12_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC2_SCL   0x174
#define  PHY_IP_MUX_REG_GRP_SEL_IIC2_SCL_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC2_SCL_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC2_SCL_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D4   0x178
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D4_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D4_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D4_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO158   0x17c
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO158_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO158_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO158_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_20   0x180
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_20_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_20_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_20_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D11   0x184
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D11_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D11_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D11_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC4_SDA   0x188
#define  PHY_IP_MUX_REG_GRP_SEL_IIC4_SDA_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC4_SDA_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC4_SDA_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D5   0x18c
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D5_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D5_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D5_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_21   0x190
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_21_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_21_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_21_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D10   0x194
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D10_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D10_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D10_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC4_SCL   0x198
#define  PHY_IP_MUX_REG_GRP_SEL_IIC4_SCL_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC4_SCL_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC4_SCL_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D6   0x19c
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D6_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D6_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D6_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO160   0x1a0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO160_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO160_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO160_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_22   0x1a4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_22_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_22_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_22_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D9   0x1a8
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D9_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D9_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D9_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D7   0x1ac
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D7_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D7_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI1_D7_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO161   0x1b0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO161_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO161_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO161_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_23   0x1b4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_23_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_23_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_23_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D8   0x1b8
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D8_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D8_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D8_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO162   0x1bc
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO162_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO162_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO162_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_24   0x1c0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_24_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_24_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_24_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO163   0x1c4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO163_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO163_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO163_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_25   0x1c8
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_25_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_25_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_25_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D16   0x1cc
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D16_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D16_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D16_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO164   0x1d0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO164_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO164_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO164_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_26   0x1d4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_26_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_26_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_26_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D17   0x1d8
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D17_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D17_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D17_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO165   0x1dc
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO165_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO165_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO165_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_27   0x1e0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_27_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_27_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_27_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D18   0x1e4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D18_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D18_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D18_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO166   0x1e8
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO166_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO166_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO166_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_28   0x1ec
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_28_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_28_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_28_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D0   0x1f0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO167   0x1f4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO167_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO167_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO167_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_29   0x1f8
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_29_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_29_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_29_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D1   0x1fc
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D1_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D1_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D1_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO168   0x200
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO168_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO168_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO168_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_30   0x204
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_30_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_30_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_30_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D2   0x208
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D2_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D2_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D2_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO169   0x20c
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO169_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO169_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO169_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_31   0x210
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_31_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_31_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_DEBUG_31_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D3   0x214
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D3_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D3_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D3_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO170   0x218
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO170_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO170_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO170_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D4   0x21c
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D4_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D4_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D4_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO171   0x220
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO171_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO171_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO171_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D5   0x224
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D5_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D5_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D5_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO172   0x228
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO172_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO172_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO172_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D6   0x22c
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D6_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D6_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D6_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK4   0x230
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK4_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK4_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK4_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO173   0x234
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO173_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO173_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO173_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D7   0x238
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D7_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D7_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VI0_D7_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK5   0x23c
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK5_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK5_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_CAM_MCLK5_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D14   0x240
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D14_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D14_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D14_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO174   0x244
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO174_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO174_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO174_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC5_SDA   0x248
#define  PHY_IP_MUX_REG_GRP_SEL_IIC5_SDA_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC5_SDA_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC5_SDA_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D14   0x24c
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D14_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D14_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D14_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D15   0x250
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D15_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D15_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D15_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO175   0x254
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO175_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO175_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO175_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC5_SCL   0x258
#define  PHY_IP_MUX_REG_GRP_SEL_IIC5_SCL_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC5_SCL_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC5_SCL_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D15   0x25c
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D15_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D15_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D15_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D16   0x260
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D16_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D16_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D16_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO176   0x264
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO176_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO176_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO176_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC6_SDA   0x268
#define  PHY_IP_MUX_REG_GRP_SEL_IIC6_SDA_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC6_SDA_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC6_SDA_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D16   0x26c
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D16_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D16_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D16_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D17   0x270
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D17_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D17_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D17_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO177   0x274
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO177_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO177_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO177_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC6_SCL   0x278
#define  PHY_IP_MUX_REG_GRP_SEL_IIC6_SCL_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC6_SCL_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC6_SCL_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D17   0x27c
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D17_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D17_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D17_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D18   0x280
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D18_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D18_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D18_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO178   0x284
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO178_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO178_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO178_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC7_SDA   0x288
#define  PHY_IP_MUX_REG_GRP_SEL_IIC7_SDA_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC7_SDA_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC7_SDA_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D18   0x28c
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D18_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D18_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D18_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D19   0x290
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D19_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D19_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D19_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO179   0x294
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO179_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO179_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO179_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC7_SCL   0x298
#define  PHY_IP_MUX_REG_GRP_SEL_IIC7_SCL_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC7_SCL_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC7_SCL_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D19   0x29c
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D19_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D19_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D19_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D20   0x2a0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D20_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D20_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D20_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO180   0x2a4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO180_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO180_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO180_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC8_SDA   0x2a8
#define  PHY_IP_MUX_REG_GRP_SEL_IIC8_SDA_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC8_SDA_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC8_SDA_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D20   0x2ac
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D20_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D20_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D20_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D21   0x2b0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D21_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D21_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D21_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO181   0x2b4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO181_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO181_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO181_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC8_SCL   0x2b8
#define  PHY_IP_MUX_REG_GRP_SEL_IIC8_SCL_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC8_SCL_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC8_SCL_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D21   0x2bc
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D21_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D21_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D21_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D22   0x2c0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D22_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D22_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D22_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO182   0x2c4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO182_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO182_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO182_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC9_SDA   0x2c8
#define  PHY_IP_MUX_REG_GRP_SEL_IIC9_SDA_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC9_SDA_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC9_SDA_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D22   0x2cc
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D22_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D22_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D22_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D23   0x2d0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D23_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D23_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D23_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO183   0x2d4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO183_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO183_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO183_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC9_SCL   0x2d8
#define  PHY_IP_MUX_REG_GRP_SEL_IIC9_SCL_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC9_SCL_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC9_SCL_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D23   0x2dc
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D23_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D23_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D23_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D24   0x2e0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D24_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D24_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D24_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SCLK   0x2e4
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SCLK_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SCLK_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SCLK_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO185   0x2e8
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO185_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO185_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO185_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_TX   0x2ec
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_TX_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_TX_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_TX_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SDI   0x2f0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SDI_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SDI_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SDI_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D24   0x2f4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D24_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D24_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D24_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D25   0x2f8
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D25_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D25_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D25_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_WSI   0x2fc
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_WSI_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_WSI_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_WSI_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO186   0x300
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO186_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO186_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO186_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_RX   0x304
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_RX_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_RX_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_RX_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SDO   0x308
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SDO_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SDO_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SDO_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D25   0x30c
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D25_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D25_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D25_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D26   0x310
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D26_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D26_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D26_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SDI   0x314
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SDI_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SDI_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SDI_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO187   0x318
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO187_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO187_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO187_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_RTS   0x31c
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_RTS_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_RTS_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_RTS_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SCK   0x320
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SCK_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SCK_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_SCK_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D26   0x324
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D26_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D26_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D26_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D0   0x328
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SDO   0x32c
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SDO_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SDO_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_SDO_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO188   0x330
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO188_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO188_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO188_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_CTS   0x334
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_CTS_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_CTS_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_UART1_CTS_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_CS_X   0x338
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_CS_X_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_CS_X_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_CS_X_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D0   0x33c
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D1   0x340
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D1_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D1_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D1_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_MCLK   0x344
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_MCLK_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_MCLK_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_I2S1_MCLK_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO189   0x348
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO189_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO189_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO189_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_UART2_TX   0x34c
#define  PHY_IP_MUX_REG_GRP_SEL_UART2_TX_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_UART2_TX_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_UART2_TX_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SDI   0x350
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SDI_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SDI_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SDI_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D1   0x354
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D1_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D1_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D1_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D2   0x358
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D2_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D2_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D2_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_MCLK   0x35c
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_MCLK_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_MCLK_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_MCLK_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO190   0x360
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO190_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO190_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO190_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_UART2_RX   0x364
#define  PHY_IP_MUX_REG_GRP_SEL_UART2_RX_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_UART2_RX_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_UART2_RX_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SDO   0x368
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SDO_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SDO_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SDO_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D2   0x36c
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D2_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D2_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D2_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D3   0x370
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D3_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D3_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D3_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SCLK   0x374
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SCLK_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SCLK_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SCLK_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO124   0x378
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO124_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO124_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO124_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_UART3_TX   0x37c
#define  PHY_IP_MUX_REG_GRP_SEL_UART3_TX_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_UART3_TX_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_UART3_TX_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SCK   0x380
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SCK_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SCK_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI2_SCK_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SCK   0x384
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SCK_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SCK_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SCK_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D3   0x388
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D3_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D3_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D3_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D4   0x38c
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D4_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D4_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D4_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_WSI   0x390
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_WSI_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_WSI_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_WSI_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO125   0x394
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO125_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO125_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO125_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_UART3_RX   0x398
#define  PHY_IP_MUX_REG_GRP_SEL_UART3_RX_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_UART3_RX_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_UART3_RX_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_CS_X   0x39c
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_CS_X_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_CS_X_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_CS_X_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_CS_X   0x3a0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_CS_X_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_CS_X_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI1_CS_X_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D4   0x3a4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D4_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D4_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D4_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D5   0x3a8
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D5_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D5_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D5_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SDI   0x3ac
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SDI_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SDI_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SDI_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO126   0x3b0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO126_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO126_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO126_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_WG1_D1   0x3b4
#define  PHY_IP_MUX_REG_GRP_SEL_WG1_D1_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_WG1_D1_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_WG1_D1_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SDI   0x3b8
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SDI_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SDI_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SDI_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC3_SDA   0x3bc
#define  PHY_IP_MUX_REG_GRP_SEL_IIC3_SDA_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC3_SDA_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC3_SDA_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D5   0x3c0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D5_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D5_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D5_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D6   0x3c4
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D6_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D6_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO0_D6_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SDO   0x3c8
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SDO_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SDO_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_I2S2_SDO_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO127   0x3cc
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO127_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO127_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_GPIO127_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_WG1_D0   0x3d0
#define  PHY_IP_MUX_REG_GRP_SEL_WG1_D0_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_WG1_D0_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_WG1_D0_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SDO   0x3d4
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SDO_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SDO_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_SPI3_SDO_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_IIC3_SCL   0x3d8
#define  PHY_IP_MUX_REG_GRP_SEL_IIC3_SCL_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_IIC3_SCL_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_IIC3_SCL_BITS   0x4
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D6   0x3dc
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D6_OFFSET 0
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D6_MASK   0xf
#define  PHY_IP_MUX_REG_GRP_SEL_VO1_D6_BITS   0x4
